1. Field of the Invention
The present invention relates to a read amplifier circuit reading data from a memory array by amplifying it, and to a semiconductor memory device employing this read amplifier circuit.
2. Description of the Background Art
A read amplifier circuit as shown in FIG. 8 has been known that reads data from a memory array by transmitting an output signal amplified by a sense amplifier to a pair of read lines GIOR and /GIOR.
Read amplifier circuit 120 includes a pair of read lines GIOR and /GIOR, P channel MOS transistors 121-125, an N channel MOS transistor 126 and a preamplifier 130. Column selection transistors 111 and 112 each formed of an N channel MOS transistor are turned on when column selection signal CSLR is set at H (logical high) level. P channel MOS transistors 121-123 are turned on when equalize signal IOEQ is set at L (logical low) level to equalize the pair of read lines GIOR and /GIOR. P channel MOS transistors 124 and 125 are turned off when preamp enable signal PAE is activated to H (logical high) level and accordingly the pair of read lines GIOR and /GIOR is cut off from preamplifier 130. N channel MOS transistor 126 is turned on when preamp enable signal PAE is activated to H (logical high) level to activate preamplifier 130 accordingly.
An output signal read from each memory cell of a memory array (not shown) is present as a potential difference on a pair of bit lines BL and /BL. The output signal amplified by a sense amplifier 110 is output to the pair of read lines GIOR and /GIOR when column selection transistors 111 and 112 are turned on by column selection signal CSLR. During the period in which column selection transistors 111 and 112 are turned on by the column selection signal and a period added as a margin, equalize signal IOEQ stays at H level and thus the pair of read lines GIOR and /GIOR is not equalized. Therefore, as column selection transistors 111 and 112 start turning on, there is generated a potential difference on the paired read lines GIOR and /GIOR according to the output signal from the paired bit lines BL and /BL. When the potential difference reaches a potential difference (usually approximately 200 mV) which can be amplified by preamplifier 130, the output signal is supplied to preamplifier 130. Following this, when preamp enable signal PAE is set at H level, preamplifier 130 is cut off from the pair of read lines GIOR and /GIOR and N channel MOS transistor 126 is turned on to be activated. Preamplifier 130 then amplifies the output signal. Equalize signal IOEQ thereafter switches from H level to L level and the pair of read lines GIOR and /GIOR is equalized.
In such a conventional circuit, the pair of bit lines BL and /BL is connected to the pair of read lines GIOR and /GIOR via column selection transistors 111 and 112. For this reason, equalization of the paired read lines GIOR and /GIOR influences the paired bit lines BL and /BL that could cause equalization of the pair of bit lines BL and /BL. If such a state occurs, data cannot be read accurately.
Further, since a plurality of pairs of read lines GIOR and /GIOR are provided, a time difference arises between transmission of column selection signal CSLR to a pair of read lines GIOR and /GIOR located close to a column decoder which outputs column selection signal CSLR and transmission thereof to a pair of read lines GIOR and /GIOR located far from the column decoder. Then, the time period from turn-on of column selection transistors 111 and 112 to generation of a potential difference on a pair of read lines GIOR and /GIOR that can be amplified by preamplifier 130 is not constant. Therefore, equalization of paired read lines GIOR and /GIOR is started after amplification of an output signal by preamplifier 130 is completed. A resultant problem is that, on a pair of read lines GIOR and /GIOR where a potential difference is generated quickly, that potential difference is large at the start of equalization and accordingly a speedily equalization is impossible.
One object of the present invention is therefore to provide a read amplifier circuit reading data at a high speed.
A read amplifier circuit according to the present invention includes a pair of read lines receiving from a pair of bit lines an output signal amplified by a sense amplifier, a preamplifier connected to the pair of read lines to amplify the output signal in response to a preamp enable signal, a cut-off circuit cutting off the pair of read lines from the preamplifier when the preamp enable signal is activated, and an equalize circuit starting equalization of the pair of read lines when the preamp enable signal is activated.
Equalization of the read line pair is started at the same time that the preamplifier starts amplifying the output signal supplied to the pair of read lines. Equalization can thus be carried out speedily and consequently high-speed reading of data is possible.
Preferably, the read amplifier circuit further includes an equalize start circuit generating an equalize start signal based on an equalize signal and the preamp enable signal, for starting equalization of the read line pair when the preamp enable signal is activated, the equalize start circuit supplying the generated equalize start signal to the equalize circuit and supplying the preamp enable signal to the cut-off circuit.
The equalize start circuit outputs the preamp enable signal and the equalize start signal to simultaneously start activation of the preamplifier and equalization of the read line pair. In this way, high-speed equalization is possible which enables high-speed reading of data. Data can also be read speedily with a small number of additional circuits.
Preferably, the read amplifier circuit further includes a pre-equalize circuit starting pre-equalization of the read line pair when the preamp enable signal is activated, and the equalize circuit equalizes the read line pair after pre-equalization of the read line pair is started by the pre-equalize circuit.
The pre-equalize circuit starts pre-equalization of the read line pair simultaneously with activation of the preamp enable signal. Accordingly, equalization can be carried out quickly and data can be read at a high speed. The data can also be read speedily with a small number of additional circuits.
A semiconductor memory device according to the present invention includes a memory array storing data, and a read amplifier circuit receiving from the memory array an output signal according to the data to amplify and output the output signal to the outside. The read amplifier circuit includes a pair of read lines receiving from a pair of bit lines an output signal amplified by a sense amplifier, a preamplifier connected to the pair of read lines to amplify the output signal in response to a preamp enable signal, a cut-off circuit cutting off the pair of read lines from the preamplifier when the preamp enable signal is activated, and an equalize circuit starting equalization of the pair of read lines when the preamp enable signal is activated.
The output signal read from the memory array is amplified by the sense amplifier and thereafter input to the pair of read lines. At the same time that the preamplifier starts amplification of the output signal, equalization of the read line pair is started and accordingly data reading cycle can be carried out faster.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.